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www.ite.com.tw feb-2009 rev:1.0 1/35 IT6603 single-link hdmi 1.3 receiver ite tech. inc. www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw feb-2009 rev:1.0 2/35 general description the IT6603 is a single-link hdmi 1.3 receiver, fully compatible with hdmi 1.3, hdcp 1.2 and backward compatible to dvi 1.0 specifications. t he IT6603 with its deep color capability (up to 36-bit) ensures robust reception of high-quality uncompressed video content, along with state-of-the-art uncompressed and compressed digital audio content such as dts-hd and dolby truehd in digital televisions and projectors. aside from the various video output formats supported, the IT6603 also receives and provides up to 8 channels of i 2 s digital audio outputs, with sampling rate up to 192khz and sample size up to 24 bits, facilitating direct connection to industry-standard low-cost audio dacs. also, an s/pdif output is provided to support up to compressed audio of 192khz frame rate. super audio compact disc (sacd) is supported at up to 8 channels and 88.2khz th rough dsd (direct stream digital ports) ports. each IT6603 comes preprogrammed with an unique hdcp key, in compliance with the hdcp 1.2 standard so as to provide secure transmission of high-definition content. us ers of the IT6603 need not purchase any hdcp keys or roms. features ? single-link hdmi 1.3 receiver ? compliant with hdmi 1.3a, hdcp 1.2 and dvi 1.0 specifications ? supporting link speeds of up to 2.25g bps (link clock rate of 225mhz). ? video output interface supporting digital video standards such as: ? 24/30-bit rgb/ycbcr 4:4:4 ? 16/20-bit ycbcr 4:2:2 ? 8/10-bit ycbcr 4:2:2 (itu bt-656) ? 24/30-bit double data rate interface (full bus width , pixel clock rate halved, clocked with both rising and falling edges) ? input channel swap ? msb/lsb swap ? bi-direction color space conversion (c sc) between rgb and ycbcr color spaces with programmable coefficients. ? up/down sampling between yc bcr 4:4:4 and ycbcr 4:2:2 ? dithering for conversion from 12-bit component to 10-bit/8-bit ? digital audio output interface supporting ? up to four i 2 s interface supporting 8-channel audio, with sample rates of 32~192 khz and www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw feb-2009 rev:1.0 3/35 sample sizes of 16~24 bits ? s/pdif interface supporting pcm, dolby digital, dts digital audio at up to 192khz frame rate ? optional support for 8-channel dsd audio up to 8 channels at 88.2khz sample rate ? support for high-bit-rate (hbr) audio such as dts-hd and dolby true hd through the four i 2 s interface or the s/pdif interface, with frame rates as high as 768khz ? automatic audio error detection for programmable soft mute, preventing annoying harsh output sound due to audio error or hot-unplug ? auto-calibrated input termination impedance provi des process-, voltage- and temperature-invariant matching to the input transmission lines. ? integrated pre-pr ogrammed hdcp keys ? intelligent, programmable power management ? 128-pin lqfp (14mm x 14mm) package www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw pin diagram 1 qe10 2 qe9 3 qe8 4 ovss 5 pclk 6 ovdd 7 qe7 8 qe6 9 qe5 10 qe4 11 ivss 12 ivdd 13 qe3 14 qe2 15 16 17 ovss 18 ovdd 19 de 20 hsync 21 vsync 22 evenodd 23 ivss 24 ivdd 25 ivdd 33 avcc18 avcc33 r0xcm 34 35 36 r0xcp avss avcc33 37 38 39 r0x0m r0x0p avss 40 41 42 avcc33 r0x1m r0x1p 43 44 45 avss avcc33 46 47 48 49 50 51 rext 52 53 54 55 56 57 ovdd 65 66 mute_dr3 67 68 dsd_dl3 69 spdif_dl2 70 ivss 71 ivdd 72 i2s0_dl0 73 i2s1_dr1 74 i2s2_dl1 75 i2s3_dr2 76 ws_dr0 77 sck_dclk 78 ovss 79 ovdd 80 mclk 81 ivss 82 ivdd 83 apvdd18 84 apvss 85 xtalout 86 xtalin 87 xtalvdd33 88 regvcc 89 qe11 ivdd ivss qe14 128 127 126 qe15 ovdd ovss 125 124 123 qe16 qe17 qe18 122 121 120 qe19 ivdd ivss 119 118 117 qe20 qe21 116 115 qe22 114 qe23 ovdd 113 ovss 112 111 110 qe26 109 qe27 108 26 pcsda 27 pcscl 28 29 30 feb-2009 rev:1.0 4/35 nc 31 ovss 32 ovdd ddcsda0 ddcscl0 r0pwr5v avss 58 59 60 61 62 63 64 r0x2m r0x2p pvss pvcc18 avcc33 avss avcc33 avss avcc33 avss avcc33 avss avcc18 nc nc nc 90 rsvdl 91 sysrstn 92 scdt 93 int# 94 95 ovdd 96 pcadr ivss ivdd qe35 ivdd 107 106 ivss qe28 105 104 qe29 103 qe30 qe31 102 ovdd 101 ovss 100 qe32 99 qe33 98 qe34 ovss IT6603 hdmi 1.3 rx lqfp-128 (top view) 97 figure 1. IT6603 pin diagram note: 1. pin51 must be connect ed with an external 500 ? smd resistor to ground. this re sistor serves to calibrate the on-chip termination impedances of all four pairs of high-speed serial links. 2. pins marked with nc should be left unconnected. www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw feb-2009 rev:1.0 5/35 pin description digital video onput pins pin name direction description type pin no. qe[35:26] qe[23:14] qe[11:2] output digital video out put pins. channel swap and msb-lsb reversal are supported through register setting. lvttl 1-3, 7-10, 13-14, 96-99, 102-105, 108-109, 112-115, 118-121, 124-125, 128 pclk output output data cloc k. the backend controller should use the rising edge of pclk to strobe qe[35:2] lvttl 5 de output data enable lvttl 17 hsync output horizontal sync. signal lvttl 18 vsync output vertical sync. signal lvttl 19 evenodd output indicates whether t he current field is even or odd for interlaced format lvttl 20 digital audio onput pins pin name direction description type pin no. xtalin input crystal clock i nput (for audio pll) lvttl 85 xtalout output crystal clock out put (for audio pll) lvttl 84 mclk output audio master clock lvttl 79 sck_dclk output i2s serial clock output, doubles as dsd clock lvttl 76 ws_dr0 output i2s word select output, doubles as dsd serial right ch0 data output lvttl 75 i2s0_dl0 output i2s serial data output, doubles as dsd serial left ch0 data output lvttl 71 i2s1_dr1 output i2s serial data output, doubles as dsd serial right ch1 data output lvttl 72 i2s2_dl1 output i2s serial data output, doubles as dsd serial left ch2 data output lvttl 73 i2s3_dr2 output i2s serial data output, doubles as dsd serial right ch2 data output lvttl 74 spdif_dl2 output s/pdif audio output, doubles as dsd serial left ch2 data output lvttl 68 mute_dr3 output mute output, doubles as dsd serial right ch3 data output lvttl 66 dsd_dl3 output dsd serial left ch3 data output lvttl 67 www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw feb-2009 rev:1.0 6/35 programming pins pin name direction description type pin no. int# output interrupt output. default active-low (5v-tolerant) lvttl 91 sysrstn input hardware reset pin. ac tive low (5v-tolerant) schmitt 89 ddcscl0 i/o ddc i2c clock for hdmi port 0 (5v-tolerant) schmitt 30 ddcsda0 i/o ddc i2c data for hdmi port 0 (5v-tolerant) schmitt 29 r0pwr5v input tmds transmitter detecti on for port 0(5v-tolerant) lvttl 31 pcscl input serial programming clock for chip programming (5v-tolerant) schmitt 25 pcsda i/o serial programming data for ch ip programming (5v-tolerant) schmitt 24 pcadr input serial programming device address select. device address is 0x90 when pcadr is pulled low, 0x92 otherwise lvttl 93 scdt output indication for active hdmi signal at input port lvttl 90 rsvdl input must be tied low via a resistor. lvttl 88 nc must be left unconnected 26,53,56, 59, hdmi analog front-end interface pins pin name direction description type pin no. r0x2p analog hdmi channel 2 positive input for hdmi port 0 tmds 48 r0x2m analog hdmi channel 2 negative input for hdmi port 0 tmds 47 r0x1p analog hdmi channel 1 positive input for hdmi port 0 tmds 44 r0x1m analog hdmi channel 1 negative input for hdmi port 0 tmds 43 r0x0p analog hdmi channel 0 positive input for hdmi port 0 tmds 40 r0x0m analog hdmi channel 0 negative input for hdmi port 0 tmds 39 r0xcp analog hdmi clock channel posit ive input for hdmi port 0 tmds 36 r0xcm analog hdmi clock channel negative input for hdmi port 0 tmds 35 rext analog external resistor for setti ng termination impedance value. should be tied to gnd via a 500 ? smd resistor. analog 51 www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw feb-2009 rev:1.0 7/35 power/ground pins pin name description type pin no. ivdd digital logic power (1.8v) power 12, 22, 23, 70, 81, 95, 107, 117, 127 ivss digital logic ground ground 11, 21, 69, 80, 94, 106, 116, 126 ovdd i/o pin power (3.3v) power 6, 16, 28, 65, 78, 92, 101, 111, 123 ovss i/o pin ground ground 4,15, 27, 64, 77, 100, 110, 122 avcc33 hdmi analog frontend power (3.3v) power 34, 38, 42, 46, 52, 55, 58, 61 avcc18 hdmi analog frontend power (1.8v) power 33, 63 avss hdmi analog frontend ground ground 32, 37, 41, 45, 54, 57, 60, 62 pvcc18 hdmi receiver pll power (1.8v) power 50 pvss hdmi receiver pll ground ground 49 apvdd18 hdmi audio pll power (1.8v) power 82 apvss hdmi audio pll ground ground 83 xtalvdd33 power for crystal oscillator (3.3v) power 86 regvcc regulator power (3.3v) for audio pll power 87 www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw functional description the IT6603 is the 2nd generation hdmi receiver and provides complete solutions for hdmi v1.3 sink systems, supporting reception and processing of deep color video and state-of-the-art digital audio such as dts-hd and dolby truehd. in addition to the standard color depth and formats supported by the previous generation (namely t he cat6011), the IT6603 with its hdm i input ports supports color depths of 10 bits and 12 bits up to 1080p. advanced processing algorithms are employed to optimize the performance of video processing such as colo r space conversion and up/down sampling. the following picture is the functional block digram of the IT6603, which describes clearly the data flow. note that only one the two inputs can be activated at a time. audio clock recovery and packet processing color space conversion & up/down sampling pclk vsync hsync de qe[35:26] sck i2s[3:0] spdif ddcscl0 ddcsda0 mute mclk ws r0x2p/m r0x1p/m r0x0p/m r0xcp/m evenodd dclk dl[3:0] dr[3:0] hdcp key i 2 c slave (ddc) config. register blocks hdcp decryption engine port 0 rcvr. afe packet data processing r0pwr5v pcscl/sda scdt int# xtalin/out qe[23:14] qe[11:2] figure 2. functional blo ck diagram of the IT6603 receiver analog frontend (rcvr. afe) the integrated tmds receiver an alog frontend macros is capable of receiving and decoding hdmi data at up to 2.25gbps (with a tmds clock of 225mhz). adaptive equaliz ation is employed to support long cables. the system firmware has total c ontrol over this thr ough register settings. feb-2009 rev:1.0 8/35 www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw while not indicated in figure 2 , the hdmi pwr5v signal of the input is also monitored by the IT6603. the system controller could poll registers to c onfirm the existence of actually connected port. figure 3. video data processi ng flow of the IT6603 video data processing flow figure 3 depicts the video data processing flow. for the pur pose of retaining maximum flexibility, most of the block enablings and path bypassings are cont rolled through register programming. please refer to IT6603 programming guide for detailed and precise descriptions. as can be seen from figure 3 , the received and recovered hdmi raw data is first hdcp-decrypted. the extracted video data then go through various pr ocessing blocks, as described in the following paragraphs, before outputting the proper video format to the backend video controller. the video processing including ycbcr up/down-sam pling, color-space conversion and dithering. depending on the selected input and output video formats, different processing blocks are either enabled or bypassed via register control. for the sake of flexibility, this is all done in software register programming. therefore, extra care should be tak en in keeping the selected output format and the corresponding video processing block selection. please refer to the it 6603 programming guide for suggested register setting. designated as qe[35:2], the output video data could take on bus width of 8 bits to 30 bits, depending on the formats and color depths. the output interface could be configured through register setting to feb-2009 rev:1.0 9/35 www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw feb-2009 rev:1.0 10/35 provide various data formats as listed in table 1 in order to cater to differ ent preferences of different backend controllers. major video processings in the IT6603 are carried out in 14 bits per channel in order to minimize rounding errors and other computational residuals t hat occur during processing. general description of video processing blocks is as follows: hdcp engine (hdcp) the hdcp engine decrypts in incoming data. pr eprogrammed hdcp keys are embedded in the IT6603. users need not worry about the purchasi ng and management of t he hdcp keys as chip advanced technology will take care of them. upsampling (ycbcr422 to ycbcr444) in cases where input hdmi video data are in ycbcr 4: 2:2 format and output is se lected as 4:4:4, this block is enabled to do the upsampling. well-design ed signal filtering is employed to avoid visible artifacts generated during upsampling. bi-directional color space conversion (ycbcr ? rgb) many video decoders only offer ycbcr outputs, while dvi 1.0 supports only rgb color space. in order to offer full compatibility between various source and si nk combination, this blo ck offers bi-directional rgb ? ycbcr color space conversion (csc). to provi de maximum flexibility, the matrix coefficients of the csc engine in the IT6603 are fully programmable. users could elect to employ their preferred conversion formula. downsampling (ycbcr444 to ycbcr422) in cases where input hdmi video data are in ycbc r 4:4:4 format and output is selected as ycbcr 4:2:2, this block is enabled to do t he downsampling. well-designed signal filtering is employed to avoid visible artifacts generated during downsampling. dithering (dithering 12-to-10 or 12-to-8) for outputing to the 10-bits / 8-bits-per-channel formats, decimation might be required depending on the exact input formats. this block performs the nece ssary dithering for decimation to prevent visible artifacts from appearing. supported output video formats table 1 lists the output video formats supported by the IT6603. the listed output pixel clock frequency in mhz is the actual clock frequency at the output pin pclk, regardless of the color depth. according to the hdmi specification v1.3, the input tmds clock frequency could be 1.25 times or 1.5 times that of the output pclk frequency, depending on the color depth: for 24-bit inputs, tmds clock frequency = 1 x pclk frequency for 30-bit inputs, tmds clock frequency = 1.25 x pclk frequency for 36-bit inputs, tmds clock frequency = 1.5 x pclk frequency www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw feb-2009 rev:1.0 11/35 the IT6603 also provides automat ic video mode detection. the system controller can elect to check out respective status registers to get the informations. output pixel clock frequency (mhz) color space video format bus width hsync/ vsync 480i 480p xga 720p 1080i sxga 1080p uxga 24 13.5 27 65 74.25 74.25 108 148.5 162 rgb 4:4:4 30 separate 13.5 27 65 74.25 74.25 108 148.5 24 13.5 27 65 74.25 74.25 108 148.5 162 4:4:4 30 separate 13.5 27 65 74.25 74.25 108 148.5 separate 13.5 27 74.25 74.25 148.5 16/20 embedded 13.5 27 74.25 74.25 148.5 separate 27 54 148.5 148.5 ycbcr 4:2:2 8/10 embedded 27 54 148.5 148.5 table 1. output video formats supported by the IT6603 notes: 1. table cells that are left blanks are those format combinations that are not supported by the IT6603. 2. output channel number is defined by the way the three color components (either r, g & b or y, cb & cr) are arranged. refer to video data bus mappings for better understanding. 3. embedded sync signals are defined by ccir-656 standard , using sav/eav sequences of ff, 00, 00, xy. 4. the lowest tmds clock freque ncy specified by the hdmi standa rd is 25mhz for 640x480@60hz. audio clock recovery and data processing the audio processing block in the hdmi sink is crucial to the system performance since human hearing is susceptive to audio imperfection. the IT6603 prides itself in outstanding audio recovery performances. in addition, the audio clock recovery pl l uses an external crystal reference so as to provide stable and reliable audio cl ocks for all audio output formats. the IT6603 supports all audio formats and interfaces sp ecified by the hdmi specification v1.3 through i 2 s, s/pdif and optional one-bit audio outputs. the one-bit audio outputs ta ke on the pins used by i 2 s outputs, so only one between the two could be activated at a time. i 2 s four i 2 s outputs are provided to support 8-channel uncompr essed audio data at up to 192khz sample rate. a coherent multiple (master) clock mclk is generated at pin 79 to facilitate proper functions of mainstream backend audio dac ics. the supported mu ltiplied factor and sample frequency as well as the resultant mclk frequencies are summarized in ta b l e 2 . www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw feb-2009 rev:1.0 12/35 audio sample frequency multiple of audio sample frequency 32khz 44.1khz 48khz 88.2khz 96khz 176.4khz 192khz 128 4.096 5.645 6.144 11 .290 12.288 22.579 24.576 256 8.192 11.290 12.288 22.579 24.576 45.158 49.152 384 12.288 16.934 18.432 33. 869 36.864 67.738 73.728 512 16.384 22.579 24.576 45. 158 49.152 90.317 98.304 640 20.480 28.224 30.720 56.448 61. 440 (112.896) (122.880) 768 24.576 33.868 36.864 67.738 73. 728 (135.475) (147.456) 896 28.672 39.514 43.008 79.027 86. 016 (158.054) (172.032) 1024 32.768 45.158 49.152 90.316 98. 304 (180.634) (196.608) table 2. output mclk frequencies (mhz) supported by the IT6603 notes: 1. the mclk frequencies in parent hesis are mclk frequencies over 100m hz. these frequencies are implemented in the IT6603 and could be output through re gister setting as well. however, t he i/o circuit of the mclk pin does not guarantee to be operating at such a high frequency under normal operation conditions. in addition, few audio backend ics such as dacs support such high mclk frequencie s. therefore, using the mclks in parenthesis is strongly discouraged. s/pdif the s/pdif output provides 2-channel uncom pressed pcm data (iec 60958) or compressed multi-channel data (iec 61937) at up to 192khz. by default the clock of s/pdif is carried within the datastream itself via coding. the IT6603 also supplie s coherent mclk in cases of s/pdif output to help ease the implementation with certain audio processing ics. one-bit audio (dsd/sacd) direct stream digital (dsd) audio is an one-bit audio format which is prescribed by super audio cd (sacd) to provide superiore aud io hearing experiences. based on t he register setting of the system controller, the IT6603 outputs dsd audio optionally through existing i 2 s output pins. a total of 8 data outputs are provided for right channels and left c hannels. refer to pin description on page 5 for detailed port-to-pin mapping. high-bit-rate audio (hbr) high-bit-rate audio is also new to the hdmi standard. it is called upon by high-end audio system such as dts-hd and dolby truehd. no specific interface is defined by the hbr standard. the IT6603 supports hbr audio in two ways. one is to employ the four i 2 s outputs simultaneously, where the original streaming ds d audio is broken into f our parallel data streams. the other is to use the s/pdif output port. the data rate in the later case is as high as 98.304mbps. a coherent mclk is generated by the IT6603 for the backend audio processors. www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw feb-2009 rev:1.0 13/35 smart audio error detection some previous hdmi sink products were re ported to generate unbearably harsh sounds during hot-plug/unplug as well as unspecified audio error. like its predecessor cat6011, the IT6603 prides itself for detecting all kinds of audio error and soft-mutes the audio a ccordingly, therefore preventing unpleasant noise from outputting. interrupt generation to provide automatic format setting, hot plug/ unplug handling and error handling, the system micro-controller should monitor th e interrupt signal output at pin 91 (int#). the IT6603 generates an interrupt signal whenever events involving t he following signals or situations occur: 1. a status change of incoming 5v power signa ls at pin 31 (corresponding to plug/unplug) 2. stable video is acquired (scdt at pin 90 is asserted) 3. events of audio errors and/or audio mute 4. events of ecc errors 5. video mode change without software intervention the hardware of t he IT6603 should be able to output some sort of displayable video data. however, this video coul d be in the wrong format or color space. also, hardware alone is not sufficient in handling the exception events listed above. the micro-controller must monitor the int# signal carefully and poll t he corresponding registers fo r optimum operation. configuration and function control the IT6603 comes with three serial programming ports : one for interfacing with micro-controller, the other two allowing access by hdmi sources th rough the two ddc channels of the hdmi links. the serial programming interface for interfacing the micro-controller is a slave interface, comprising pcscl (pin 25) and pcsda (pin 24). the micro-cont roller uses this interface to monitor all the statuses and control all the functions. two device addresses are available, depending on the input logic level of pcadr (pin 93) . if pcadr is pulled high by the user, the device address is 0x92 . if pulled low, 0x90 . the ddc i 2 c interface is present at ddcscl0 (pin 30) & ddcsda0 (pin 29). with the interfaces, the IT6603 responds to the access of hdmi sources via the ddc channels. hdmi sources use the interfaces to perform hdcp authentication with the IT6603. all serial programming interf aces conform to standard i 2 c transactions and operate at up to 100khz. www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw feb-2009 rev:1.0 14/35 electrical specifications absolute maximum ratings symbol parameter min. typ max unit ivdd core logic supply voltage -0.3 2.5 v ovdd i/o pins supply voltage -0.3 4.0 v avcc33 hdmi analog frontend power -0.3 4.0 v avcc18 hdmi analog frontend power -0.3 2.5 v pvcc18 hdmi receiver pll power -0.3 2.5 v apvdd18 hdmi audio pll power -0.3 2.5 v xtalvdd33 power for crystal oscillator -0.3 4.0 v regvcc power for regulator -0.3 4.0 v v i input voltage -0.3 ovdd+0.3 v v o output voltage -0.3 ovdd+0.3 v t j junction temperature 125 c t stg storage temperature -65 150 c esd_hb human body mode esd sensitivity 2000 v esd_mm machine mode esd sensitivity 200 v notes: 1. stresses above those listed under absolute maximum rati ngs might result in permanent damage to the device. functional operation conditions symbol parameter min. typ max unit ivdd core logic supply voltage 1.6 1.8 2.0 v ovdd i/o pins supply voltage 2.97 3.3 3.63 v avcc33 hdmi analog frontend power 2 3.135 3.3 3.465 v avcc18 hdmi analog frontend power 1.6 1.8 2.0 v pvcc18 hdmi receiver pll power 1.6 1.8 2.0 v apvdd18 hdmi audio pll power 1.6 1.8 2.0 v xtalvdd33 power for crystal oscillator 3.0 3.3 3.6 v regvcc power for regulator 3.0 3.3 3.6 v v ccnoise supply noise 100 mv pp t a ambient temperature 0 25 70 c ja junction to ambient thermal resistance c/w notes: 1. avcc33, avcc18, pvcc18 and apvdd18 should be regulated. 2. avcc33 supplies the termination voltage. theref ore the range is specif ied by the hdmi standard. www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw feb-2009 rev:1.0 15/35 operation supply cu rrent specification symbol parameter pclk typ max unit 27mhz 38 42 ma 74.25mhz 86 95 ma 148.5mhz 147 162 ma i ivdd_op ivdd current under normal operation 222.75mhz 185 204 ma 27mhz 6 7 ma 74.25mhz 18 20 ma 148.5mhz 26 29 ma i ovdd_op ovdd current under normal operation (with 20pf capacitive output loading) 222.75mhz 29 32 ma 27mhz 49 54 ma 74.25mhz 64 71 ma 148.5mhz 79 88 ma i avcc18_op avcc18 current under normal operation (with input vdiff= 750 mv) 222.75mhz 97 105 ma 27mhz 83 89 ma 74.25mhz 83 89 ma 148.5mhz 83 89 ma i avcc33_op avcc33 current under normal operation (with input vdiff= 750 mv) 222.75mhz 83 89 ma 27mhz 5 5 ma 74.25mhz 13 14 ma 148.5mhz 22 24 ma i pvcc18_op pvcc18 current under normal operation 222.75mhz 32 35 ma 27mhz 6 6 ma 74.25mhz 6 6 ma 148.5mhz 6 6 ma i apvdd18_op apvdd18 current under normal operation 222.75mhz 6 6 ma i xtalvdd33 xtalvdd33 current under normal operation (all speeds) 1 1 ma i regvcc regvcc current under normal operation (all speeds) 0 0 ma 27mhz 473 561 mw 74.25mhz 641 764 mw 148.5mhz 820 983 mw pw total_op total power consumption under normal operation 3 222.75mhz 949 1132 mw notes: 1. typ: ovdd=avcc33=xtal vdd33=regvcc=3.3v, ivdd=av cc18=pvcc18=apvd d18=1.8v max: ovdd=avcc33= xtalvdd33=regvcc= 3.6v, ivdd=avcc18=pv cc18=apvdd18=1.98v 2. pclk=27mhz: 480p with 48khz/8-channel audio, pclk=74.25mhz: 1080i with 192khz/8-channel audio, pclk=148.5mhz: 1080p with 192khz/8-channel audio, pclk=222.75mhz: 1080p@ 36-bit deep color with 192khz/8-channel audio 3. pw total_op are calculated by multiplying the supply currents with their corresponding supply voltage and summing up all the items. www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw feb-2009 rev:1.0 16/35 4. dc electrical specification under functional operation conditions symbol parameter pin type conditions min. typ max unit v ih input high voltage 1 lvttl 2.0 v v il input low voltage 1 lvttl 0.8 v v t switching threshold 1 lvttl 1.5 v v t- schmitt trigger negative going threshold voltage 1 schmitt 0.8 1.1 v v t+ schmitt trigger positive going threshold voltage 1 schmitt 1.6 2.0 v v ol output low voltage 1 lvttl i ol =2~16ma 0.4 v oh output high voltage 1 lvttl i oh =-2~-16ma 2.4 i in input leakage current 1 all v in =5.5v or 0 5 a i oz tri-state output leakage current 1 all v in =5.5v or 0 10 a i ol serial programming output sink current 2 schmitt v out =0.2v 4 16 ma v diff tmds input differential swing 3 tmds r ext =500 150 1200 mv notes: 1. guaranteed by i/o design. 2. the serial programming output ports are not real o pen-drain drivers. sink curr ent is guaranteed by i/o design under the condition of driving the out put pin with 0.2v. in a real i 2 c environment, multiple devices and pull-up resistors could be present on the same bus, rendering t he effective pull-up resistance much lower than that specified by the i 2 c standard. when set at maximum current, the serial programming output ports of the IT6603 are capable of pulling down an effect ive pull-up resistance as low as 500 connected to 5v termination voltage to the standard i 2 c v il . when experiencing insufficient low level pr oblem, try setting the current level to higher than default. refer to IT6603 programming guide for proper register setting. 3. limits defined by hdmi 1.3a standard audio ac timing specification under functional operation conditions symbol parameter conditions min. typ max unit f s_i2s i 2 s sample rate up to 8 channels 32 192 khz f s_spdif s/pdif sample rate 2 channels 32 192 khz f s_dsd dsd sample rate up to 8 channels 96 khz f xtal external audio crystal frequency 1 300ppm accuracy 24 27 28.5 mhz notes: 1. the IT6603 is designed to work in default with a 27mhz crystal for audio func tions. crystals of other frequencies within the designated functional r ange mandate certain register prog ramming for proper functioning. www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw feb-2009 rev:1.0 17/35 video ac timing specification under functional operation conditions symbol parameter conditions min. typ max unit t pixel pclk pixel clock period 1 4.44 40 ns f pixel pclk pixel clock frequency 1 single-edged clocking 25 225 mhz t cde pclk dual-edged clock period 2 8.88 40 ns f cde pclk dual-edged clock frequency 2 dual-edged clocking 25 112.5 mhz t pduty pclk clock duty cycle 40% 60% notes: 1. fpixel is the inverse of tpixel . operating frequency range is given here while the actual video clock frequency should comply with all video timing standards. refer to table 1 for supported video timings and corresponding pixel frequencies. 2. 12-bit dual-edged clocking is supported up to 74.5m hz of pclk frequency, which covers 720p/1080i. 3. all setup time and hold time specific ations are with respect to the latc hing edge of pclk selected by the user through register programming. www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw feb-2009 rev:1.0 18/35 video data bus mappings the IT6603 supports various output data mappi ngs and formats, including those with embedded control signals only. corresponding r egister setting is to be taken care of for any chosen input data mappings. refer to IT6603 programming guide for detailed instruction. color space video format bus width h/vsync clocking table 24/30 seperate 1x 4 rgb 4:4:4 24/30 seperate 0.5x, dual-edged 4 24/30 seperate 1x 4 4:4:4 24/30 seperate 0.5x, dual-edged 4 seperate 1x 5 16/20 embedded 1x 6 seperate 2x 8 ycbcr 4:2:2 8/10 embedded 2x 7 table 3. output video format supported by the IT6603 www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw feb-2009 rev:1.0 19/35 rgb 4:4:4 and ycbcr 4:4:4 with separate syncs rgb ycbcr pin name 30-bit 24-bit 30-bit 24-bit qe2 b0 nc cb0 nc qe3 b1 nc cb1 nc qe4 b2 b0 cb2 cb0 qe5 b3 b1 cb3 cb1 qe6 b4 b2 cb4 cb2 qe7 b5 b3 cb5 cb3 qe8 b6 b4 cb6 cb4 qe9 b7 b5 cb7 cb5 qe10 b8 b6 cb8 cb6 qe11 b9 b7 cb9 cb7 qe14 g0 nc y0 nc qe15 g1 nc y1 nc qe16 g2 g0 y2 y0 qe17 g3 g1 y3 y1 qe18 g4 g2 y4 y2 qe19 g5 g3 y5 y3 qe20 g6 g4 y6 y4 qe21 g7 g5 y7 y5 qe22 g8 g6 y8 y6 qe23 g9 g7 y9 y7 qe26 r0 nc cr0 nc qe27 r1 nc cr1 nc qe28 r2 r0 cr2 cr0 qe29 r3 r1 cr3 cr1 qe30 r4 r2 cr4 cr2 qe31 r5 r3 cr5 cr3 qe32 r6 r4 cr6 cr4 qe33 r7 r5 cr7 cr5 qe34 r8 r6 cr8 cr6 qe35 r9 r7 cr9 cr7 hsync hsync hsync hsync hsync vsync vsync vsync vsync vsync de de de de de table 4. rgb & ycbcr 4:4:4 mappings these are the simpliest formats, with a complete defin ition of every pixel in each clock period. timing examples of 30-bit rgb 4:4:4 is depicted in figure 4 respectively. www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw figure 4. 30-bit rgb 4:4:4 timing diagram feb-2009 rev:1.0 20/35 www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw feb-2009 rev:1.0 21/35 ycbcr 4:2:2 with separate syncs 20-bit 16-bit pin name pixel#2n pixel#2n+1 pixel#2n pixel#2n+1 qe2 nc nc nc nc qe3 nc nc nc nc qe4 nc nc nc nc qe5 nc nc nc nc qe6 nc nc nc nc qe7 nc nc nc nc qe8 nc nc nc nc qe9 nc nc nc nc qe10 nc nc nc nc qe11 nc nc nc nc qe14 y0 y0 nc nc qe15 y1 y1 nc nc qe16 y2 y2 y0 y0 qe17 y3 y3 y1 y1 qe18 y4 y4 y2 y2 qe19 y5 y5 y3 y3 qe20 y6 y6 y4 y4 qe21 y7 y7 y5 y5 qe22 y8 y8 y6 y6 qe23 y9 y9 y7 y7 qe26 cb0 cr0 nc nc qe27 cb1 cr1 nc nc qe28 cb2 cr2 cb0 cr0 qe29 cb3 cr3 cb1 cr1 qe30 cb4 cr4 cb2 cr2 qe31 cb5 cr5 cb3 cr3 qe32 cb6 cr6 cb4 cr4 qe33 cb7 cr7 cb5 cr5 qe34 cb8 cr8 cb6 cr6 qe35 cb9 cr9 cb7 cr7 hsync hsync hsync hsync hsync vsync vsync vsync vsync vsync de de de de de table 5. mappings of ycbcr 4:2:2 with separate syncs ycbcr 4:2:2 format does not have one complete pixel for every clock period. luminace channel (y) is given for every pixel, while the two chroma channel s are given alternatively on every other clock period. the average bit amount of y is twice that of cb or cr. depending on the bus width, each component could take on different lengths. the de period should contain an even number of clock periods. figure 5 gives a timing example of 20-bit ycbcr 4:2:2. www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw figure 5. 20-bit ycbcr 4:2:2 with separate syncs figure 6. 16-bit ycbcr 4:2:2 with separate syncs feb-2009 rev:1.0 22/35 www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw feb-2009 rev:1.0 23/35 ycbcr 4:2:2 with embedded syncs 20-bit 16-bit pin name pixel#2n pixel#2n+1 pixel#2n pixel#2n+1 qe2 nc nc nc nc qe3 nc nc nc nc qe4 nc nc nc nc qe5 nc nc nc nc qe6 nc nc nc nc qe7 nc nc nc nc qe8 nc nc nc nc qe9 nc nc nc nc qe10 nc nc nc nc qe11 nc nc nc nc qe14 y0 y0 nc nc qe15 y1 y1 nc nc qe16 y2 y2 y0 y0 qe17 y3 y3 y1 y1 qe18 y4 y4 y2 y2 qe19 y5 y5 y3 y3 qe20 y6 y6 y4 y4 qe21 y7 y7 y5 y5 qe22 y8 y8 y6 y6 qe23 y9 y9 y7 y7 qe26 cb0 cr0 nc nc qe27 cb1 cr1 nc nc qe28 cb2 cr2 cb0 cr0 qe29 cb3 cr3 cb1 cr1 qe30 cb4 cr4 cb2 cr2 qe31 cb5 cr5 cb3 cr3 qe32 cb6 cr6 cb4 cr4 qe33 cb7 cr7 cb5 cr5 qe34 cb8 cr8 cb6 cr6 qe35 cb9 cr9 cb7 cr7 hsync embedded embedded embedded embedded vsync embedded embedded embedded embedded de embedded embedded embedded embedded table 6. mappings of ycbcr 4:2:2 with embedded syncs similar to ycbcr 4:2:2 with separate sync. the onl y difference is that the syncs are now non-explicit, i.e. embedded. bus width could be 16-bit, 20-bit. figure 7 gives a timing example of 20-bit ycbcr 4:2:2 and figure 8 that of 16-bit. note that while "emb edded syncs" implies t hat neither de nor h/vsync are required, the IT6603 optionally output th ese signals via proper regi ster setting to ease the design for some backend processors. www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw figure 7. 20-bit ycbcr 4:2:2 with embedded syncs figure 8. 16-bit ycbcr 4:2:2 with embedded syncs feb-2009 rev:1.0 24/35 www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw feb-2009 rev:1.0 25/35 ccir-656 format 10-bit 8-bit pin name pclk#2n pclk#2n+1 pclk#2n pclk#2n+1 qe2 nc nc nc nc qe3 nc nc nc nc qe4 nc nc nc nc qe5 nc nc nc nc qe6 nc nc nc nc qe7 nc nc nc nc qe8 nc nc nc nc qe9 nc nc nc nc qe10 nc nc nc nc qe11 nc nc nc nc qe14 c0 y0 nc nc qe15 c1 y1 nc nc qe16 c2 y2 c0 y0 qe17 c3 y3 c1 y1 qe18 c4 y4 c2 y2 qe19 c5 y5 c3 y3 qe20 c6 y6 c4 y4 qe21 c7 y7 c5 y5 qe22 c8 y8 c6 y6 qe23 c9 y9 c7 y7 qe26 nc nc nc nc qe27 nc nc nc nc qe28 nc nc nc nc qe29 nc nc nc nc qe30 nc nc nc nc qe31 nc nc nc nc qe32 nc nc nc nc qe33 nc nc nc nc qe34 nc nc nc nc qe35 nc nc nc nc hsync embedded embedded embedded embedded vsync embedded embedded embedded embedded de embedded embedded embedded embedded table 7. mappings of ccir-656 the ccir-656 format is yet another va riation of the ycbcr formats. the bus width is further reduced by half compared from the previous ycbcr 4:2:2 forma ts, to either 8-bit or 10-bit. to compensate for the halving of data bus, pclk frequency is doubled. with the double-rate output clock, luminance channel (y) and chroma channels (cb or cr) are alternated. the syncs signals are embedded in the y-channel. normally this format is used only fo r 480i, 480p, 576i and 576p. the IT6603 supports ccir-656 format of up to 720p or 1080i, with the doubled -rate clock running at 148.5mhz. ccir-656 www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw format supports embedded syncs only. figure 9 and figure 10 give examples of 10-bit and 8-bit ccir-656 respectively. note that while "embedded syn cs" implies that neither de nor h/vsync are required, the IT6603 optionally output these signals vi a proper register setting to ease the design for some backend processors. figure 9. 10-bit ccir-656 figure 10. 8-bit ccir-656 feb-2009 rev:1.0 26/35 www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw feb-2009 rev:1.0 27/35 ccir-656 + separate syncs 10-bit 8-bit pin name pclk#2n pclk#2n+1 pclk#2n pclk#2n+1 qe2 nc nc nc nc qe3 nc nc nc nc qe4 nc nc nc nc qe5 nc nc nc nc qe6 nc nc nc nc qe7 nc nc nc nc qe8 nc nc nc nc qe9 nc nc nc nc qe10 nc nc nc nc qe11 nc nc nc nc qe14 c0 y0 nc nc qe15 c1 y1 nc nc qe16 c2 y2 c0 y0 qe17 c3 y3 c1 y1 qe18 c4 y4 c2 y2 qe19 c5 y5 c3 y3 qe20 c6 y6 c4 y4 qe21 c7 y7 c5 y5 qe22 c8 y8 c6 y6 qe23 c9 y9 c7 y7 qe26 nc nc nc nc qe27 nc nc nc nc qe28 nc nc nc nc qe29 nc nc nc nc qe30 nc nc nc nc qe31 nc nc nc nc qe32 nc nc nc nc qe33 nc nc nc nc qe34 nc nc nc nc qe35 nc nc nc nc hsync hsync hsync hsync hsync vsync vsync vsync vsync vsync de de de de de table 8. mappings of ccir-656 + separate syncs this format is not specified by ccir-656. it's si mply the previously mentioned ccir-656 format plus separate syncs. examples of this mode are given in figure 11 and figure 12 . www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw figure 11. 10-bit ccir-656 + separate syncs pixel0 ~ pixel1 ... blank pclk de h/vsync sav pixel2 ~ pixel3 .... ff qe[35:26] qe[23:16] qe[15:2] ff cb pix0 [7:0] y pix0 [7:0] cr pix0 [7:0] y pix1 [7:0] cb pix2 [7:0] y pix2 [7:0] 00 00 xy cr pix2 [7:0] y pix3 [7:0] figure 12. 8-bit ccir- 656 + separate syncs feb-2009 rev:1.0 28/35 www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw rgb 4:4:4 and ycbcr 4:4:4 triggered with 0.5x pclk at dual edges the bus mapping in this format is the same as that of rgb 4:4:4 and yc bcr 4:4:4 with separate syncs. the only difference is that the output video clock (pclk) is now halved in frequency. the data are in turn to be latched in with both the rising and falling edges of the 0.5x pclk. r pix0 r pix1 r pix2 r pix3 r pix4 r pix5 r pix6 .... g pix0 g pix1 g pix2 g pix3 g pix4 g pix5 g pix6 .... b pix0 b pix1 b pix2 b pix3 b pix4 b pix5 b pix6 .... val val val qe[35:26] qe[23:14] qe[11:2] val val val blank pixel0 pixel2 pixel1 pixel3 pixel5 pixel4 pixel6 ... pclk de h/vsync val val val val val val val val val blank figure 13. 30-bit rgb 4: 4:4 dual-edges triggered with 0.5x pclk figure 14. 24-bit rgb 4: 4:4 dual-edges triggered with 0.5x pclk feb-2009 rev:1.0 29/35 www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw system design consideration the IT6603 is a very high-speed interface chip. it receives tmds differential signals at as high as 2.25gbps and output ttl signals at up to 148.5mhz with 30-bit data bus. at such high speeds any pcb design imperfection could lead to co mpromised signal integrity and hence degraded performance. to get the optimum performance the system designers s ould follow the guideline below when designing the applicati on circuits and pcb layout. 1. pin 50 (pvcc18) and pin 49 ( pvss) should be supplied with clean power: ferrite-decoupled and capacitively-bypassed, since they supply the power fo r the receiver pll, which is a crucial block in terms of receiving quality. excess power noise might degrade the system performance. 2. it is highly recommended that all power pins ar e decoupled to ground pins via capacitors of 0.01uf and 0.1uf. low-esl capacitors are prefered. genera lly these capacitors should be placed on the same side of the pcb with the IT6603 and as close to the pins as possible, preferably within 0.5cm from the pins. it is also reco mmended that the power and ground traces run relatively short distances and are connected directly to respecitve power and ground planes through via holes. figure 15. layout example for decoupling capacitors. 3. the IT6603 supports 30-bit output bus running at as high as 148.5mhz. to maintain signal integrity and lower emi, the following gui delines should be followed: a. employ 4-layer pcb design, where a ground or power plane is directly placed under the signal buses at middle layes. the ground and power planes underneath these buses should be continuous in order to provide a solid re turn path for em-wave introduced currents. b. whenever possible, keep all ttl signal trac es on the same layer with the IT6603 and the feb-2009 rev:1.0 30/35 www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw feb-2009 rev:1.0 31/35 backend scalers. c. ttl output traces to the scaler should be kept as short as possible d. 33? resistors could be placed in series to the out put pins. this slow down the signal rising edges, reduces current spikes and lower the reflections. e. the pclk signal should be kept away from other signal traces to avoid crosstalk interference. a general guideline is 2x the diel ectric thickness. for example, if the dielectric layer between the signal layer and the immediate power/ground laye r is 7 mil, then the pclk trace should be kept at least 14 mil away fr om all other signal traces. 4. the characteristic impedance of all diff erential pcb traces should be kept at 100 ? all the way from the hdmi connector to the IT6603. this is crucial to the system performance at high speeds. when layouting these differential tr ansmission lines, the following gu idelines should be followed: a. the signals traces should be on the outside layers (top layer or bottom layer) while beneath it there should be a cont inuous ground plane in order to maintain the so-called micro-strip transmission line st ructure, giving stable and well -defined characteristic impedances. b. carefully choose the width and spacing of the differential transmission lines as their characteristic impedance depends on various para meters of the pcb: trace width, trace spacing, copper thickness, dielectric constan t, dielectric thickness, etc. careful 3d em simulation is the best way to derive a co rrect dimension that enables a nominal 100 ? differential impedance. c. cornering, through holes, cro ssing and any irregular signal routi ng should be minimized so as to prevent from disrupting the em field and creating discontinuity in characteristic impedance. d. the IT6603 should be placed as close to the hdmi connector as possible. if the distance between the chip and the connector is under 2 cm, t he reflections could be kept small even if the pcb traces do not have an 100? characteristic impedance. the extra signal attenuation contributed by the pcb traces could be minimized, too. 5. special care should be taken when adding discrete esd devices to all differential pcb traces (rx2p/m, rx1p/m, rx0p/m, rxcp/m). the IT6603 is designed to provide esd protection for up to 2kv at these pins, which is good enough to prevent damages during assembly. to meet the system emc specification, external di screte esd diodes might be added. bu t note that adding discrete esd diodes inevitably add capacitive loads, therefore degr ade the electrical performance at high speeds. if not chosen carefully, these diodes coupled with le ss-than-optimal layout wo uld prevent the system from passing the sink tmds-diffe rential impedance test in the hdmi compliance test (test id 8-8). one should only use low-capacitance esd diode to protect these high-speed pins. commercially available devices such as semtech's rclamp0524p that take into consideration of all aspects of designing and protecting high-speed tr ansmission lines are recommended. (http://www.semtech.com/ www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw products/product-detail.js p?navid=h0,c2,c222,p3028) . figure 16. layout exam ple for high-speed tmds differential signals 6. by default pin 51 (rext) should be connected to ground via a 500 ? /1% precision smd resistor to provide for receiver termination calibration. if this pin is to be left open, be sure to set the bit 6 of register 0x6a to '1' in order to disable the termination calibra tion. disabling the termination calibration would leave the value of terminat ion impedance subject to process, supply voltage and temperature variation, sometimes rendering it out of specification and degrading the performanc e. therefore it is highly recommended that this calibration function is left turned-on and a 500 ? /1% resistor is connected between pin 51 and ground. the resistor should be placed as close to the IT6603 as possible. feb-2009 rev:1.0 32/35 www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw package dimensions figure 17. 128-pin lqfp package dimensions feb-2009 rev:1.0 33/35 www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw classification reflow profiles reflow profile pb-free assembly average ramp-up rate (ts max to tp) 3 /second max. preheat -temperature min(ts min ) -temperature max(ts max ) -time(ts min to ts ts max ) 150 200 60-180 seconds time maintained above: -temperature(t l ) -time(t l ) 217 60-150 seconds peak temperature(tp) 260 +0 /-5 time within 5 of actual peak temperature(tp) 20-40 seconds ramp-down rate 6 /second max. time 25 to peak temperature 8 minutes max. note: all temperature refer to topside of the pack age, measured on the package body surface. feb-2009 rev:1.0 34/35 www.datasheet.co.kr datasheet pdf - http://www..net/
IT6603 www.ite.com.tw carrier tray dimensions feb-2009 rev:1.0 35/35 www.datasheet.co.kr datasheet pdf - http://www..net/

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